1. Field of the Invention
The present invention relates, generally, to an apparatus for identifying defects in identical electronic assemblies situated therein, and more particularly, to such an apparatus for identifying defects in control computers and switching installations.
2. Description of the Prior Art
The document U.S. Pat. No. 4,176,258 A discloses an electronic apparatus for identifying defects in identical assemblies situated therein, in which the assemblies or their associated defect identification circuits are connected to one another via a unidirectional line. In this case, the transmission direction is fixed via predetermined inputs. As a result, all but one defect identification circuit of the identical assemblies are activated and defect identification is effected in a relatively simple manner.
The document DE 42 33 569 C2 discloses an information processing unit having a plurality of processor modules which each have a defect monitoring circuit. In this case, the processor modules are constructed identically, wherein addresses and data are compared in the event of memory accesses on the processor buses for the purpose of identifying defects in the processor modules. The outlay on circuitry for effecting such defects identification is, however, extremely.
Furthermore, the document DE 197 17 686 A1, discloses a circuit arrangement for a motor vehicle control system constructed from two identically constructed circuits each having a microprocessor system. The input data is processed in a redundant manner in this case. In order to evaluate and monitor both the input data and the intermediate results obtained in the course of data processing, the microprocessor systems are connected to one another via a communications device.
The document U.S. Pat. No. 5,627,839 furthermore discloses so-called xe2x80x9cboundary scan cellsxe2x80x9d. For bidirectional signals, mutually isolated scan cells are used in this case, wherein it is possible to test electrical connections between integrated circuits and external circuits and, thus to identify defects (short circuits, interruptions, . . . ).
Moreover, the literature reference xe2x80x9cFxc3xa4rber, G.: Prozexcex2rechentechnik, [Process computing technology], Berlin et al.: Springer-Verlag, 1979, pages 73-77 and 140-142xe2x80x9d discloses a circuit for improving reliability in process computer systems. In this case, in a dual-computer system, the two subsystems record measured values and output control signals which are subsequently compared.
In order to identify defects in electronic assemblies, it is known that, in particular in control computers and switching installations, central functions, for reasons of redundancy, are usually carried out by two identical electronic assemblies whose functional capability is monitored. The two assemblies, designed as ASICs for example, carry out the same functions identically at each point in time. In order to monitor the functional capability of the assemblies, one respective assembly sends to the other assembly a signature which includes a plurality of bits and which is assigned to it; i.e., a test data structure which represents the activity of the respective assembly and is formed, for example, from memory addresses, data and control signals. If both assemblies exhibit full functional capability, the signatures assigned to them are identical. After the respective signature has been sent from one assembly to the other, a comparison is made; i.e., the signature assigned to one assembly is compared with the signature sent by the other assembly. If there is a deviation between the signatures, a diagnosis is started and the defective assembly is switched off.
In this case, the respective signatures are sent from one assembly to the other via two parallel bundles of lines. FIG. 3 shows such an arrangement for a line pair. However, this arrangement also requires a high outlay due to the provision of double the number of interfaces; e.g., assembly connector and ASIC pins.
The present invention, therefore, is directed to providing an apparatus for identifying defects in electronic assemblies with a low outlay on circuitry.
Accordingly, the present invention teaches an electronic apparatus having a first assembly and a second assembly, which is identical to the first assembly; a bidirectional line, which connects the first and second assemblies to one another and is coupled to a voltage source; a first and a second test data output register respectively assigned to an assembly; a first and a second line driver, which are respectively assigned to an assembly, connected to the line via an interface and designed in such a way that, in response to a signal generated by the test data output register, the line is connected to ground or isolated therefrom; a first and a second line receiver, which are respectively assigned to an assembly and connected to the line via the interface; and a first and a second evaluation device, which are respectively assigned to an assembly and designed in such a way that lack of correspondence between the signals of the first and second test data output registers is detected. The outlay on circuitry is reduced in so far as there is only one bundle of lines between the assemblies and, as a result, the number of interfaces and/or connections of the respective assembly is reduced.
The line driver has a pull-up resistor which connects the voltage source to the line. Such an arrangement means that, on the one hand, a level 1 is applied to the line in a simple manner and, on the other hand, reflections on the line are avoided.
Furthermore, the line driver has a buffer, in particular a buffer with open collector, whose output only becomes active when the state of the line is to be changed from the level 1 to the level 0.
The outlay on circuitry can be reduced further by the line receiver also having a buffer or being formed therefrom, which is matched to the buffer of the power driver. This measure reduces the number of component types in the apparatus of the present invention.
The outlay on circuitry is reduced further by the line driver and the line receiver having a bidirectional buffer of integrated design. This measure facilitates the miniaturization of the apparatus according to the present invention.
Preferably, the assemblies including the test data output register, the line driver, the line receiver and the evaluation device are designed as ASICs. The apparatus of the present invention can, thus, be matched to customer-specific requirements in a relatively simple manner.
In particular, the electronic apparatus of the present invention is suitable for use in a processor for switching systems since in these systems, in order to ensure defect-free operation, the central functions are, in each case, carried out by two identical assemblies.